The present invention relates to an integrated circuit, and, more particularly, to a semiconductor device structure and methods of manufacturing the same.
In the art of fabricating semiconductors, it is important that the surface of a semiconductor wafer be planarized in order to meet the requirements of optical projection lithography. Two common techniques used to achieve planarity on a semiconductor surface are the Spin-On Glass (SOG) etchback process and the Chemical Mechanical Polishing (CMP) process. Although both processes improve planarity on the surface of a semiconductor wafer, CMP has been shown to have a higher level of success in improving global planarity. The assurance of planarity is crucial to the lithography process as the depth of focus of the lithography process is often inadequate for surfaces which do not have a consistent height.
The amount of material removed during the CMP process has been shown to be dependent upon the pattern density of the topography of the layers being polished.
Dummy patterns may be added in order to equalize the pattern density of topography on the surface of a wafer. Referring to FIGS. 1A˜1C, a conventional method of inserting dummy patterns is illustrated. FIG. 1A illustrates an exemplary IC layout 100A, wherein the shaded parts represent conductive features 110 and 115. Using FIG. 1B as an example, a dummy cell 101a and an accompanying blank space 103a are organized as a dummy unit 10a. The dummy unit 10a is repeatedly laid over IC layout 100A for forming IC layout 100B comprising dummy patterns in the open area thereof. For example, a dummy unit 10a is first positioned at a corner of IC layout 100B. Other dummy units are then subsequently laid over IC layout 100B. If the dummy cell is adjacent to conductive feature 110 or 115, the corresponding dummy unit is removed. Using FIG. 1C as an example, the blocks marked with slant lines are dummy cells that are allowed to be inserted, and the blocks marked with cross lines are dummy cells that are not allowed to be inserted because they are adjacent to the conductive feature. Dummy units 10a, 10b, 10c, and 10d, forming a dummy structure 10, are added to IC layout 100C. Referring to FIG. 1D, after insertion of dummy units, IC layout 100D comprises conductive features 110 and 115, and dummy structure 10.
The described conventional method has several disadvantages. First, it is time consuming to lay numerous dummy units over an IC layout. Second, it is difficult to achieve a suitable pattern density by inserting dummy units of the same size and shape. A large amount of computing resource is required to perform the conventional method. Additionally, it is difficult to estimate the achieved pattern density before the dummy insertion is complete. Failing to achieve a suitable pattern density causes problems in subsequent planarization processes.
Hence, there is a need for systems and methods that address problems arising from the existing technology.